are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog f.

that require sophisticated timer/counter, PWM, sync signal processing, A/D converter, and multi-master IIC-bus support w.

Table 1-1. S3C8639/C863A Pin Descriptions Pin Names P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0
  –P3.3 P3.4
  –P3.7 Pin Type I/O Pin Description General-purpose, 8-bi.

S3P8615

S3P8629

S3P8095

S3P80E5

S3P80E7

S3P80F7

S3P80F9

S3P80G7

S3P80G9

S3P821A

S3P8245

S3P8249

S3P825